The present invention relates in general to circuit simulation and, more particularly, to a method of modeling a plurality of serially coupled circuit cells with a distributed serial load.
Integrated circuit designs are becoming more complex while the time allocated for the design effort is decreasing. To satisfy these conflicting concerns, circuit designers are turning to libraries of standard cells from which to build the overall design. A standard cell is a pre-designed and pre-tested functional block that can be plugged into a circuit. The standard cell library includes a myriad of functional blocks such NAND and NOR gates, multiplexers, memories, counters, multipliers, flipflops, etc. The standard cell can be as simple as an inverter and as complex as an arithmetic logic unit. Thus, standard cell libraries of pre-defined circuit functions are the building blocks for more complex circuits. Building the circuit with cells from a library is very efficient especially for ASICs or other standard cell designs.
The library typically includes simulation data for each standard cell. The simulation data characterizes the standard cell by parameters such as manufacturing process, supply voltage, temperature, edge transition rate, and output load. The characterization parameters are useful when running a computer aided design (CAD) simulation such as SPICE to test the various features before a physical embodiment is built. The SPICE simulator solves a number of voltage and current equations to determine the performance of the cell. Each equation is a function of many other voltages and currents in other nodes and transistors. The integrated circuit is thus mathematically modeled in the computer simulator whereby the design parameters are verified or manipulated to work out the inevitable problems associated with different embodiments before proceeding with the cost and effort of building an actual circuit.
Characterizing the output load of the cell is an important concern of the present invention. In the prior art, the output load of a cell is typically modeled by placing a single lumped capacitor at the output of the cell. The lumped capacitor models the effective capacitive load, e.g. number of devices being driven, as seen by the output driver of the cell. A common design rule for standard cell construction is to buffer each and every input and output of the cell. The buffering assures that the output of any cell is loaded by no more than the input buffer of the next cell(s). The output load of one buffer is unaffected by any output load of any cell it is driving. Unfortunately, a lumped effective capacitive load does not accurately model situations where the output load of one cell is influenced by the load on subsequent cells. For example, if a first circuit cell drives a second circuit cell that has no buffered input and no buffered output, then the loading on the output of the second circuit cell has an effect on the output load of the first circuit cell. A single lumped capacitor does not accurately model such unbuffered cells that do have an influence on the prior cells.
Hence, a need exists to accurately model circuit cells where the output load is influenced by the load on subsequent unbuffered cells.